Implementation of Digital Phase Locked Loop Using CMOS Technology

AUTHOR(S)

K.B.Meena Kumari, Goobala Kavya, P.Indu Sree, D.Anuvardhan Reddy, D.Balaji

DOI: https://doi.org/10.46647/ijetms.2023.v07si01.022

ABSTRACT
The requirement for low power and rapid circuits are expanding in present day hardware. The generation of carrier and locking of phase have become significant for transceiver circuits. The frequency divider which is dependent on the phase locked loop (PLL) is a fundamental building block of the transceiver. The frequency divider that produces carrier for the down- conversion/up-conversion functions, it works at high frequency, and it expends a massive portion of the whole power of the circuit. The frequency divider dependent on phase locked loop (PLL) comprises of voltage-controlled oscillator (VCO), phase detector, loop filter and frequency divider. The voltage-controlled oscillator (VCO) and frequency divider expends the utmost power. This paper presents a CMOS digital phase locked loop which is proposed with low power utilization voltage-controlled oscillator (VCO) circuit andfrequency divider circuit using 45nm CMOS technology

Page No: 143 - 148

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How to Cite This Article:
K.B.Meena Kumari, Goobala Kavya, P.Indu Sree, D.Anuvardhan Reddy, D.Balaji . Implementation of Digital Phase Locked Loop Using CMOS Technology . ijetms;7(s1):143-148. DOI: 10.46647/ijetms.2023.v07si01.022