HIGH-EFFICIENT VLSI ARCHITECTURE FOR THREE OPERAND BINARY ADDER

AUTHOR(S)

Abineetha M, Aparna Bhuvanesvari L, Aswini G, Charulatha N B, Dr A Kirthika

DOI: https://doi.org/10.46647/ijetms.2023.v07i02.063

ABSTRACT
This paper presents a VLSI architecture for a three-operand binary adder. The proposed design is based on a carry-select adder (CSLA) and Han-Carlson (HCA) adder. Carry-select adder is known for its high speed and low power consumption. The architecture uses a novel carry-in selection scheme that reduces the number of logic gates required for carry generation. Additionally, Han-Carlson (HCA), a parallel prefix two-operand adder, can also be used for three-operand addition, significantly reducing the critical path delay at the cost of supplementary hardware. In addition to perform the three-operand binary addition with significantly less space and low power consumption, a novel high-speed and area-efficient adder architecture is suggested. This architecture uses pre-compute bitwise addition followed by carry-selection computation logic. The design also includes a parallel processing unit that allows the efficient computation for multiple operands of multiple results simultaneously. The proposed architecture has been implemented in Verilog HDL and synthesized using a 32nm CMOS technology. The simulation results show that the design achieves high performance with low power consumption. Additionally, the proposed design can be easily scaled to handle larger operands without sacrificing performance or area overhead. When compared to the current three-operand adder approaches, the suggested adder achieves the lowest ADP and PDP.

Page No: 543 - 549

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How to Cite This Article:
Abineetha M, Aparna Bhuvanesvari L, Aswini G, Charulatha N B, Dr A Kirthika . HIGH-EFFICIENT VLSI ARCHITECTURE FOR THREE OPERAND BINARY ADDER . ijetms;7(2):543-549. DOI: 10.46647/ijetms.2023.v07i02.063