2023, Volume 7 Special Issue 1
Design a CMOS Flash ADC Architecture With Low Power and High Speed Operation
AUTHOR(S)
K.S. Deveswari, Shaik Ali Ahammad, Parlapalli Sahithya, Karnam Nagendra Tharun sudha, Vasantha Lava Sai
DOI: https://doi.org/10.46647/ijetms.2023.v07si01.011
ABSTRACT
Analog-to-digital converters (ADCs) are essential to the present digitized world because they process analog signals. Several embedded, communication, and signal processing systems make use of ADCs. In this study, a high speed, low power CMOS flash ADC architecture is shown. The proposed architecture is implemented using 180 nm CMOS technology. The principle of most significant bit (MSB) creation is employed with a switching reference voltage. A low power TIQ comparator has been used to generate the range of reference voltages. The reference voltage is switched by a control circuit at the halfway voltage of the input signal (Vk). The current architecture uses 2N-1 comparators as Compared to the 2N-1 comparators of a conventional flash ADC. The recommended flash ADC also has a low power encoder. The circuits are designed using TANNER EDA and the performance is analyzed with a total power consumption of 595.78µW with an input signal frequency of 1GHz
Page No: 71 - 79
References:
[1] The Flash ADC [A Circuit for All Seasons], B. Razavi, IEEE Solid-State Circuits Magazine, 9–13, 2017,
[2] Flash ADC architecture, Alex Stojcevski H.P.Le., Jugdutt Singh, Aladin Zayegh, Electronics Letters, 39, 6, 501–502, 2003,
[3] Future directions in silicon ICs for RF personal communications, P. R. Gray and R. G. Meyer, Proceedings of the IEEE 1995 Custom Integrated Circuits Conference, 83–90, 1995, IEEE
[4] New power saving design method for CMOS flash ADC, Chia-Chun Tsai, Kai-Wei Hong, Yuh-Shyan Hwang, Wen-Ta Lee and Trong-Yen Lee, The 2004 47th Midwest Symposium on Circuits and Systems, 371– 374, 2004, IEEE
[5] A multi step A/D converter family with efficient architecture, M. K. Mayes and S. W. Chin, IEEE Journal of Solid-State Circuits, 24, 6, 1492-1497, 1989, IEEE
[6] A low-power 1 MHz, 25mW 12-bit time-interleaved analog-to-digital converter, M. K. Mayes and S. W. Chin and L. L. Stoian, IEEE Journal of Solid-State Circuits, 31, 2, 169-178, 1996, IEEE
[7] Implementation of low power flash ADC by reducing comparators, Megha, R and Pradeepkumar, KA, 2014 International Conference on Communication and Signal Processing, 443–447, 2014, IEEE
[8] A SoC based low power 8-bit flash ADC in 45 nm CMOS technology, Guha, S and Sharma, P and Dutta, R, Proceedings of the International Conference on Advances in Electronics, Electrical and Computer Science Engineering (EEC), 2012
[9] Implementation of Flash ADC using Multisim Technology, Raghavendra, R and Hariprasad, SA, International Journal of Computer Trends and Technology (IJCTT), 4, 6, 1825–1830, 2013
[10] Design of four bit Flash ADC using clocked digital comparator, Madankar, Abhishek and Palsodkar, Prachi, 2013, Citeseer
[11] A 45nm flash analog to digital converter for low voltage high speed system on chips, Ghai, Dhruva and Mohanty, Saraju P and Kougianos, Elias, Proceedings of the 13th NASA Symposium on VLSI Design, 3, 2007
[12] High speed comparator for flash ADC and UWB application in 130nm CMOS technology, Marvast, MJ Taghizadeh and Ali, MA Mohd, 2009 IEEE International Conference on Signal and Image Processing Applications, 402–405, 2009, IEEE
[13] CMOS digital integrated circuits: analysis and design, Leblebici, Yusuf, 1996, McGraw-Hill College
[14] Thermometer-to-adjacent binary encoder, Knierim, Daniel G, 1988, march ” 22”, Google Patents, US Patent 4,733,220
How to Cite This Article:
K.S. Deveswari, Shaik Ali Ahammad, Parlapalli Sahithya, Karnam Nagendra Tharun sudha, Vasantha Lava Sai
. Design a CMOS Flash ADC Architecture With Low Power and High Speed Operation
. ijetms;7(s1):71-79. DOI: 10.46647/ijetms.2023.v07si01.011