Different Leakage Power Reduction Techniques Comparison in CMOS VLSI Design

AUTHOR(S)

Ms. S. Bhavani, R. Rasi, S. Hibza, M. Samatha B. Veerendra Reddy, K. Vinay

DOI: https://doi.org/10.46647/ijetms.2023.v07si01.016

ABSTRACT
Gadgets consuming less power have risen as a well-known subject in the cutting-edge electronics industry. Decrease in consumption of power makes a device increasingly dependable and productive. As a result, CMOS innovation turned out to be most popular for low power utilization gadgets. Cutback on the voltage supply decreases the dynamic power loss quadratically and the leakage power linearly. Weak inversion current due to leakage is a prime candidate for standing power utilization. Since the feature sizes continue to reduce it has caused an exponential rise in weak inversion current due to leakage thanks to the reduction of sub-threshold voltage. As stated in the previous works, leakage power dissipation sooner or later may tower above the total power consumption as the size of technological features reduce to nano-meter scheme in submicron technologies. This paper is aimed to bring a thorough analysis and comparison of various leakage power reduction techniques

Page No: 104 - 111

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How to Cite This Article:
Ms. S. Bhavani, R. Rasi, S. Hibza, M. Samatha B. Veerendra Reddy, K. Vinay . Different Leakage Power Reduction Techniques Comparison in CMOS VLSI Design . ijetms;7(s1):104-111. DOI: 10.46647/ijetms.2023.v07si01.016