Error Detection and Correction Using Minimal Parity Based on Matrices

AUTHOR(S)

P.Anil Kumar, R.Supriya, M.Sravya, G.Tejaswi, M.Sharmila Bai

DOI: https://doi.org/10.46647/ijetms.2023.v07si01.019

ABSTRACT
Multiple cell upsets are caused by improvements in complementary metal oxide semiconductor (CMOS) technology (MCUs). MCUs had been a difficult problem for data storage in memory for numerous applications because of the radiation particles. Because of their simple encoding and decoding, error correction codes are one of the approaches that are employed more frequently to safeguard memories. Typically, MCUs have an impact on nearby memory bits. Consequently, a productive strategy would be one that would find and rectify as many neighboring bits as possible. Matrix-based code has only one drawback: it requires a large number of parity bits to facilitate error correction in memories. We reduced the number of parity bits in this document to address the flaw. When compared to other existing strategies, the suggested technique provides an equivalent error-correction capability with a lower parity bit count. Area, power, and delay time have all decreased, along with the total number of parity bits, by 30%, and by 1.12%, 33.59%, and 55.46%, respectively. These factors render the suggested strategy for memory protection effective and efficient. Applications where parity bits and speed are strictly regulated can employ this technique.

Page No: 124 - 130

References:

[1] E. Ibe, H. Taniguchi, Y. Yahagi, K. Shimbo and T. Toba, “Impact of scaling on neutron-induced soft error rate in SRAMs From a 250 nm to a 22 nm Design Rule”, IEEE Trans. on Electron Devices, Vol. 57 , No. 7, pp. 1527-1538, July. 2010.
[2] Shivani Tambatkar, Siddharth Narayana Menon, Sudarshan.V, M.Vinodhini and N.S.Murty , “Error Detection and Correction in Semiconductor Memories using 3D Parity Check Code with Hamming Code ,” International Conference on Communication and Signal Processing, April 6-8, 2017, India.
[3] Shanshan Liu, Liyi Xiao, Jie Li, Yihan Zhou, and Zhgang Mao, “Low Redundancy Matrix-Based codes for Adjacent Error Correction with Parity ,” 18th International Symposium on Quality Electronic Design (ISQED),2017
[4] Sunita M.S and Kanchana Bhaaskaran , “ Matrix code based Multiple Error Correction Technique for N-bit memory data” , International Journal of VLSI design Communication Systems (VLSICS) Vol.4, No.1, February. 2013.
[5] Paromita Raha, M Vinodhini, N. S. Murty ”Horizontal-Vertical Parity and Diagonal Hamming Based Soft Error Detection and Correction for Memories,” Jan. 05 – 07, 2017, Coimbatore, INDIA.
[6] Costas A. Argyrides, Pedro Reviriego, Dhiraj K. Pradhan, and Juan Antonio Maestro ,“Matrix-Based Codes for Adjacent Error Correction in storing data,” IEEE Transactions on Nuclear Science, Vol. 57, No. 4, August. 2010.
[7] N. N. Mahatme, B. L. Bhuva, Y. P. Fang, and A. S. Oates, “Impact of strained-Si PMOS transistors on SRAM soft error rates,” IEEE Trans. Nucl. Sci. , Vol. 59, No. 4, pp. 845–850, August. 2012.

How to Cite This Article:
P.Anil Kumar, R.Supriya, M.Sravya, G.Tejaswi, M.Sharmila Bai . Error Detection and Correction Using Minimal Parity Based on Matrices . ijetms;7(s1):124-130. DOI: 10.46647/ijetms.2023.v07si01.019