International Journal Of Engineering Technology And Management Sciences

AUTHOR(S)

ATTAR MEHARAJ BANU, SYED NOORULLAH

DOI: https://doi.org/10.46647/ijetms.2023.v07i01.019

Page No: 109 - 119

ABSTRACT
In current world of computations, data encryption is of prominent importance. Many algorithms were developed for data encryption and decryption to prevent hacking. The Advanced Encryption Standard (AES) is one of the data encryption techniques. Two famous kinds of hardware implementation techniques are pipelining and loop-unrolling techniques. In pipelining, registers are inserted between each combinational processing element so that each input data block can be processed simultaneously in each processing element. In this work, a pipelined implementation of AES encryption algorithm is developed. The number of rounds of AES-128 encryption is 10 and an architecture implementing this cipher is called fully pipelined, when all data blocks of 10 rounds can be processed simultaneously. In the loop-unrolling technique one or multiple rounds of the algorithm are processed in the same clock cycle. Here only one round of the algorithm is implemented as a combinational processing element and a data register is also used to store the result obtained in the previous clock cycle. In this work, a128-bit AES is implemented and for each round of AES encryption, a different sub-key is used as the round key, which is produced by the key schedule algorithm based on the loop-unrolled technique, to produce the required sub-key for each round is done. The no of I/O, Slices in the proposed work are 386, 229 respectively with Spartan6 fpga with a minimum period of 5.813ns,maximum Frequency of 172.031MHz, minimum input arrival time before clock of 4.823ns,maximum output required time after clock of 5.588ns, throughput of 2.2Gbps. The no of I/O, Slices are 387, 264 respectively with Artix7 fpga with a minimum period of 3.397ns, maximum Frequency of 294.366MHz, minimum input arrival time before clock of 1.649ns, maximum output required time after clock of 1.669ns, throughput of 3.77Gbps.

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How to Cite This Article:
ATTAR MEHARAJ BANU, SYED NOORULLAH. IMPLEMENTATION FPGA BASED IMPLEMENTATION OF 128-BIT AES ALGORITHM USING VHDL. ijetms;7(1):109-119. DOI: 10.46647/ijetms.2023.v07i01.019