International Journal Of Engineering Technology And Management Sciences

AUTHOR(S)

M. Surekha, V. HariKrishna, B. MadhuSudhan Reddy, G.Tejaswini, I.Rajasekhar, K.Divya

DOI: https://doi.org/10.46647/ijetms.2023.v07i02.033

ABSTRACT
Static CMOS and Domino CMOS Circuits are significantly used in high performance VLSI system. Designing a circuit with low power, high speed performance is one of the challenging aspects. In modern VLSI systems area efficient devices are utmost popular because most of the devices are becoming portable. This paper proposes One- bit full adder circuit is designed using CMOS based on mirror logic and Domino CMOS also designed based on same logic with LTSPICE at 180nm technology with 1.8V supply. This method provides better power and delay.

Page No: 283 - 288

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How to Cite This Article:
M. Surekha, V. HariKrishna, B. MadhuSudhan Reddy, G.Tejaswini, I.Rajasekhar, K.Divya . Efficient Approaches to Design Full Adder Using Domino Logic Technique . ijetms;7(2):283-288. DOI: 10.46647/ijetms.2023.v07i02.033