International Journal of Engineering Technology and Management Sciences

2023, Volume 7 Issue 3

Fabrication of CNTFET Simulation Using Cadence Virtuoso

AUTHOR(S)

Kiran D.R., Naveen Kumar Y., Prajwal D. Nadig, Tejas H.R., Varun Jois K.P., Dr. Sindhu Sree M., Dr. Pavithra G., Dr. T.C.Manjunath

DOI: https://doi.org/10.46647/ijetms.2023.v07i03.65

ABSTRACT
In this paper, the fabrication of CNTFET with the help of simulation using cadence virtuoso is presented. The process of fabricating Carbon Nanotube Field-Effect Transistors (CNTFETs) is a sophisticated task that demands great attention to detail. To aid in the design and optimization of CNTFET fabrication processes, simulation tools are often utilized. CNTFET fabrication simulations generally involve modeling the physical and chemical processes of creating the carbon nanotube channel, as well as the device's metal contacts and other components. Simulation tools such as COMSOL Multiphysics or Lumerical are used to model the mechanical, thermal, and electrical properties of the materials involved, and to predict how they will behave during fabrication. An essential challenge in CNTFET fabrication is obtaining precise control over the nanotube placement and orientation, which can be addressed through modeling the nanotube growth and optimizing the growth parameters to achieve the desired properties. Furthermore, simulations can assist in optimizing the process parameters for depositing metal contacts on the nanotubes, which is critical for achieving good device performance. Overall, simulation tools play a vital role in the CNTFET fabrication process, enabling researchers to optimize the device design and fabrication parameters for improved performance and yield. The work done & presented in this paper is the result of the mini-project work that has been done by the first sem engineering students of the college and as such there is little novelty in it and the references are being taken from various sources from the internet, the paper is being written by the students to test their writing skills in the starting of their engineering career and also to test the presentation skills during their mini-project presentation. The work done & presented in this paper is the report of the assignment / alternate assessment tool as a part and parcel of the academic assignment of the first year subject on nanotechnology & IoT.

Page No: 476 - 479

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How to Cite This Article:
Kiran D.R., Naveen Kumar Y., Prajwal D. Nadig, Tejas H.R., Varun Jois K.P., Dr. Sindhu Sree M., Dr. Pavithra G., Dr. T.C.Manjunath .Fabrication of CNTFET Simulation Using Cadence Virtuoso . ijetms;7(3):476-479. DOI: 10.46647/ijetms.2023.v07i03.65

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