Design Of Three Stage Comparator Using 90nm Technology

AUTHOR(S)

Lakshmi N., Dr. Pavithra G., Dr. T.C.Manjunath

DOI: https://doi.org/10.46647/ijetms.2023.v07i06.008

ABSTRACT
In this paper, the design of three stage comparator using 90nm technology is presented. The comparator is one of the block that limits the speed of the converter, its optimization is crucial and important and design of Analog-to-Digital Converter (ADC),is the speed limiting element in comparator. It describes the schematic design of a three stage CMOS comparator to achieve lower power dissipation and a lower offset voltage, with high-speed operation. Test structure of the comparator are designed using GPDK 90nm. The three-stage comparator makes it possible to use NMOS input pairs in both the regeneration stage and the amplification stage, further increasing the speed. Furthermore, in the modified version of three-stage comparator, a CMOS input pair is adopted at the amplification stage. Simulation results are obtained and it shows that the proposed design can work under 1.8V supply, with an offset voltage of 200mV, and thus, an innovative circuit technique is implemented to overcome these limitations. The work carried out is the mini-project that is a part & parcel of the curriculum in the 2nd semester.

Page No: 40 - 43

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How to Cite This Article:
Lakshmi N., Dr. Pavithra G., Dr. T.C.Manjunath . ijetms;7(6):40-43. DOI: 10.46647/ijetms.2023.v07i06.008